K.
Analog Layout Engineer
Overview
$2.33/hr · Part Time (3hr/day)
Education:
B.Sc. in Engineering, Electrical Electronic and Communicatio...
Last Active:
Today
Joined:
September 02, 2026
Profile Description
Analog Layout Engineer with hands-on experience in PMIC layout design and physical verification using 180nm CMOS technology. Proficient in Cadence Virtuoso, DRC/LVS verification, and advanced 16nm FinFET technology.
Skills
Python
Less than a year
Analog IC Layout
1 years
PMIC Layout
1 years
Cadence Virtuoso
1 years
Layout Verification
1 years
180nm BCDMOS
1 years
16nm FinFET
1 years
CMOS Technology
1 years
Tapeout Support
1 years
Analog Block Design
1 years
Experience
Ulkasemi Pvt. LTD
Assistant Engineer(Analog Layout Design)
May 2026 – Present
Worked on PMIC projects with multiple tapeout experiences. Designed analog blocks including ADC, Charge Pump, Comparator, Band Gap, Amplifiers, Current Mirror, and Power on Reset using 180nm BCDMOS and High voltage technologies.
Ulkasemi Pvt. LTD
Trainee Engineer
November 2025 – April 2026
Trained in 16nm FinFET technology, layout of various analog blocks, and debugging LVS and solving DRC issues.
Education
B.Sc. in Engineering, Electrical Electronic and Communication Engineering
Military Institute of Science and Technology
2021 - 2025
HSC, Science
Dhaka City College
2018 - 2020
SSC, Science
Dhanmondi Govt. Boys’ High School
2017 - 2018
Client Reviews
Basic Information
Age
23
Gender
Male
Location
Dhaka, BangladeshResume
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